The present invention relates to an encoder and a decoder for use in a digital transmission of video signals, and more particularly to an encoder and a decoder for respectively encoding and decoding video signals including halftones.
Video signals obtained by scanning a pictorial advertisement, a photograph or the like with a scanner usually are analog signals having halftones. One of the prior art methods of converting such an analog video signals into binary signals and to compression-encode them is to express pseudo-halftone signals by an ordered dither method. This method generates a bit sequence of "1" and "0" and run-length encode the consecutive black and white lengths of this signal sequence.
The ordered dither method uses an n-by-n dither matrix storing thresholds for conversion into a bit sequence consisting of "1" and "0" codes. The thresholds periodically vary in the directions of the main scan and the subscan. Thus, an analog video signal sequence representing gray is converted into a bit sequence of periodic black and white pixels. Accordingly, the run-length is short and the number of runs is great Therefore, the compression efficiency of the run-length encoding is extremely low. Meanwhile, the U.S. Pat. No. 4,475,127 reveals a logic converter circuit for a run-length encoding, at a high compression efficiency, of signal sequences which are obtained by the ordered dither method.
This logic converter circuit converts a signal sequence consisting of "1" and "0" codes, in which white and black pixels periodically alternate, into a new signal sequence in which the run lengths of "1" and "0" are greater. The converter includes a circuit for generating a signal indicating whether the sum of n signals is an odd or an even number. These n signals comprise an input signal and signals produced by delaying that input signal by 1, 2, 3 . . . , (n-1) sampling periods.
However, the aforementioned logic converter circuit disclosed in the U.S. Pat. No. 4,475,127 utilizes the periodicity inherent in the bit sequence. No common logic converter circuit can be used for a bit sequence digitized with threshold values which vary in different periods, i.e. a bit sequence/digitized with dither matrices of different sizes. Therefore, the logic inverter has to be redesigned for a different dither matrix size.